Test MP+dmb.sy+ctrl-data-[ws-rf]-addr-pos

AArch64 MP+dmb.sy+ctrl-data-[ws-rf]-addr-pos
"DMB.SYdWW Rfe DpCtrldR DpDatadW WsLeave RfBack DpAddrdR PosRR Fre"
Cycle=Rfe DpCtrldR DpDatadW WsLeave RfBack DpAddrdR PosRR Fre DMB.SYdWW
Relax=
Safe=Rfe Fre PosRR DMB.SYdWW DpAddrdR DpDatadW DpCtrldR [WsLeave,RfBack]
Prefetch=0:x=F,0:y=W,1:y=F,1:x=T
Com=Rf Fr Rf
Orig=DMB.SYdWW Rfe DpCtrldR DpDatadW WsLeave RfBack DpAddrdR PosRR Fre
{
0:X1=x; 0:X3=y;
1:X1=y; 1:X3=z; 1:X5=a; 1:X9=x;
2:X1=a;
}
 P0          | P1                  | P2          ;
 MOV W0,#1   | LDR W0,[X1]         | MOV W0,#2   ;
 STR W0,[X1] | CBNZ W0,LC00        | STR W0,[X1] ;
 DMB SY      | LC00:               |             ;
 MOV W2,#1   | LDR W2,[X3]         |             ;
 STR W2,[X3] | EOR W4,W2,W2        |             ;
             | ADD W4,W4,#1        |             ;
             | STR W4,[X5]         |             ;
             | LDR W6,[X5]         |             ;
             | EOR W7,W6,W6        |             ;
             | LDR W8,[X9,W7,SXTW] |             ;
             | LDR W10,[X9]        |             ;
Observed
    y=1; x=1; a=2; 1:X8=1; 1:X6=1; 1:X10=0; 1:X0=1;
and y=1; x=1; a=1; 1:X8=1; 1:X6=1; 1:X10=0; 1:X0=1;
and y=1; x=1; a=2; 1:X8=1; 1:X6=2; 1:X10=0; 1:X0=0;
and y=1; x=1; a=2; 1:X8=1; 1:X6=1; 1:X10=0; 1:X0=0;
and y=1; x=1; a=1; 1:X8=1; 1:X6=1; 1:X10=0; 1:X0=0;